1. Field of the Invention
The present invention relates in general to Global Positioning System (GPS) receivers, and in particular to a GPS Radio Frequency (RF) front end Integrated Circuit (° C.) with a frequency plan for improved integrability.
2. Description of the Related Art
The design choice of using a relatively high clock frequency such as 48•fo for GPS processing allows speed advantages in minimizing GPS signal acquisition time-to-first-fix and reacquisition. As an example, U.S. Pat. No. 5,897,605, which is herein incorporated by reference, teaches such techniques for a GPS Processor ASIC. Unfortunately, significant harmonic power of the clock at a frequency near the GPS satellite carrier will exist and tend to jam or desensitize the GPS RF Front End. Specifically, for the case of a 48•fo clock, where fo=1.023 MHz, the 32nd harmonic of such a clock lies at 1536•fo, which is only 4•fo below the GPS signal at 1540•fo. If the frequency plan of the receiver is not chosen judiciously, then the aforementioned 32nd harmonic will not be rejected by the RF or IF filter of the RF Front End IC, and loss of receiver sensitivity may result.
It can be seen, then, that there is a need in the art for a GPS receiver that has a frequency plan that will avoid self-jamming problems due to harmonics of the clock frequency.